As AI workloads continue to surge and data centers struggle to keep pace with rising power demands, a new semiconductor startup is stepping into the spotlight with a bold promise to cut chip energy consumption in half. PowerLattice, founded in 2023 by former engineers from Qualcomm, NUVIA, and Intel, has emerged from stealth with a breakthrough chiplet and a powerful endorsement from one of the industry\u2019s most influential figures.<\/p>\n\n\n\n
On Monday, the company announced a $25 million Series A round led by Playground Global and Celesta Capital, pushing total funding to $31 million. Among the investors is former Intel CEO Pat Gelsinger, who now serves as a general partner at Playground Global.<\/p>\n\n\n\n
Gelsinger described PowerLattice\u2019s work as a rare and highly technical effort to solve one of the semiconductor industry\u2019s toughest challenges: delivering power more efficiently at the chip level. He called the engineering team \u201ca dream team of power delivery,\u201d emphasizing that very few groups are capable of working on problems this complex.<\/p>\n\n\n\n
During PowerLattice\u2019s initial pitch at Playground\u2019s offices earlier this year, CEO Dr. Peng Zou and his team were visibly excited to meet Gelsinger, even asking for a selfie. But beyond the light moment, Gelsinger was struck by their technology and the potential impact it could have on future chip designs.<\/p>\n\n\n\n
The startup\u2019s innovation centers on a small power-delivery chiplet that brings energy significantly closer to the processor. By reducing the distance power must travel, the chiplet minimizes energy loss, delivering far greater efficiency than current solutions. While the concept sounds simple, engineering such a system is a formidable challenge, which makes PowerLattice\u2019s claims even more notable.<\/p>\n\n\n\n
Two years after its founding, PowerLattice has already reached a major development milestone. Its first batch of chiplets is now being produced by TSMC, the world\u2019s leading chip manufacturer, with an unnamed customer currently testing the technology\u2019s performance.<\/p>\n\n\n\n
PowerLattice expects to expand access to additional customers in the first half of 2026, a timeline that aligns with rising industry interest in energy-efficient chip architectures. Because power consumption is becoming a bottleneck for AI compute growth, the company\u2019s potential customer base includes major players like Nvidia, Broadcom, and AMD, as well as AI-focused chipmakers such as Cerberus, Grok, d-Matrix, and NextSilicon.<\/p>\n\n\n\n
Although most chipmakers maintain internal teams dedicated to power-efficiency improvements, Gelsinger believes PowerLattice\u2019s approach offers something distinctly new. He predicts companies may adopt a blended strategy, combining traditional methods with PowerLattice\u2019s chiplet, but expects the startup to secure meaningful market traction once broader testing begins.<\/p>\n\n\n\n